(QuickLogic: San Jose, CA) -- QuickLogic Corp., a leading provider of embedded FPGA (eFPGA) hard IP and ruggedized FPGAs, has announced the integration of the Synopsys Synplify synthesis tool into its FPGA user tools. This integration enhances QuickLogic’s design environment by accelerating FPGA-based design cycles, improving PPA and enabling engineers to work in a familiar design environment.

With Synplify’s well-established synthesis capabilities now accessible within QuickLogic’s design flow, engineers gain powerful tools to optimize their projects, leveraging improved quality of results (QoR) and resource efficiency. The integration of Synplify, an industry-standard synthesis solution, into QuickLogic’s eFPGA IP and FPGA platforms offers engineers several key advantages.

Enhanced QoR: Synplify’s synthesis algorithms maximize logic efficiency, performance, power consumption, and silicon area, delivering optimized implementations for customers targeting QuickLogic eFPGA hard IP.

Familiar design flow: With the industry-leading FPGA synthesis tool, eFPGA IP and FPGA developers are already familiar with Synplify, enabling a faster, smoother synthesis cycle that helps engineers meet tight timelines.

“We’re excited to integrate Synplify, which aligns perfectly with our mission to deliver high-performance eFPGA IP and FPGA solutions quickly and efficiently,” says Mao Wang, senior director of product management at QuickLogic. “This addition strengthens productivity and quality of results for customers who are looking to get the highest performance and area efficiency in their designs.”

Rakesh Jain, senior director of product management at Synopsys, says, “Synplify has long been recognized for its strength in FPGA synthesis, and we’re excited to see its capabilities extend to QuickLogic’s innovative eFPGA Hard IP solutions. By integrating Synplify, QuickLogic enables engineers to realize high-quality, efficient designs that are optimized for PPA.”